A 1024-Channel 268 nW/pixel 36x36 μm 2 /ch Data-Compressive Neural Recording...

Paper

Abstract

This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with $36 \mu m$ pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves $9.8 \mu V_{RMS}$ input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.

Analysis

Paper intelligence

Summary

This paper introduces a novel neural recording integrated circuit (IC) designed for high-bandwidth brain-computer interfaces, employing data compression during digitization to manage data volume.

Key findings

The IC features a 32x32 MEA with 36 μm pixel pitch.
It consumes 268 nW per pixel from a single 1V supply.
Achieves 9.8 μV_RMS input-referred noise and 0.3-5kHz bandwidth.
Employs wired-OR-based compression to discard baseline samples and reconstruct spike samples.

Methods

Lossy compression during digitization.
Wired-OR-based compression.
32x32 MEA design.
Single 1V supply operation.

Limitations

The abstract does not explicitly state limitations.

Applications

High-bandwidth brain-computer interfaces.
Neural recording.

Confidence100%

Discovery

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Source record

Publication metadata

Authors: MoonHyung Jang; Wei-Han Yu; Changuk Lee; M.T. Hays; Pingyu Wang; Nick Vitale; Pulkit Tandon; Pumiao Yan; Pui‐In Mak; Youngcheol Chae; E. J. Chichilnisky; Boris Murmann; Dante G. Muratore
Published: Jun 11, 2023
DOI: 10.23919/vlsitechnologyandcir57934.2023.10185288
Paper type: journal article
Source: Openalex

DOI OpenAlex