A 1024-Channel 268-nW/Pixel 36×36 μm²/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain–Computer Interfaces

This article presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain–computer interfaces (BCIs). The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146 $\times $ on average while allowing the reconstruction of spike samples. The recording array consists of pulse-position modulation (PPM)-based active digital pixels (ADPs) with a global single-slope (SS) analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 $\times $ 32 array) with a pixel pitch of 36 $\mu \text{m}$ that can be directly matched to a high-density micro-electrode array (MEA). The pixel achieves 7.4- $\mu \text{V}_{\text {rms}}$ input-referred noise with a −3-dB bandwidth of 300 Hz–5 kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 $\times $ 36 $\mu \text {m}^{{2}}$ ) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

Authors

MoonHyung Jang; M.T. Hays; Wei-Han Yu; Changuk Lee; P. Caragiulo; Athanasios T. Ramkaj; Pingyu Wang; AJ Phillips; Nicholas Vitale; Pulkit Tandon; Pumiao Yan; Pui‐In Mak; Youngcheol Chae; E. J. Chichilnisky; Boris Murmann; Dante G. Muratore

Published

Dec 29, 2023

Journal or venue

IEEE Journal of Solid-State Circuits

DOI

10.1109/jssc.2023.3344798

Paper type

journal article

Source

Openalex